1. Field of the Invention
The present invention relates to a semiconductor device having a protective circuit and, more particularly, to the structure of a new protective circuit disposed in a semiconductor device for protecting an internal circuit of the semiconductor device.
2. Description of the Related Art
Semiconductor device generally has a protective circuit for protecting the internal circuit of the semiconductor device against an electrostatic destruction caused by electrostatic charge entering from outside through input/output terminals.
FIG. 1 shows a circuit diagram of a conventional semiconductor device including a protective circuit connected between a power source terminal (Vdd terminal) 201 and a ground terminal (Vss terminal) 202 for protecting the semiconductor device.
An internal circuit 208 having a specific function and including a plurality of CMOS transistors is connected via a source line (Vdd line) and a ground line (Vss line) to the Vdd terminal 201 and the Vss terminal 202. A protective circuit 204 is connected between the internal circuit 208 and I/O terminals including the Vdd terminal 201 and the Vss terminal 202 at the location between the I/O terminals and the internal circuit 208. The protective circuit 204 is comprised of an n-channel MOS transistor 211 which is connected between the source line Vdd and the ground line Vss, and a p-channel MOS transistor 221 which is connected between the source line Vdd and the ground line Vss in parallel to the n-channel MOS transistor 211. Gate and source of the n-channel MOS transistor 211 are directly connected to the ground line Vss, and drain thereof is directly connected to the source line Vdd. Gate and source of the p-channel MOS transistor 221 are directly connected to the source line Vdd, and drain thereof is directly connected to the ground line Vss.
When a positive high voltage (for example, a noise voltage having a magnitude that causes electrostatic destruction of MOS transistors in the internal circuit) enters through the Vdd terminal 201, the internal circuit 208 is protected by a sequence of operations of the protective circuit 20a against the postive high voltage. More specifically, the n-channel MOS transistor 211, upon drain-to-source breakdown thereof, assumes a bipolar transistor function thereby to cause a current to flow from the Vdd terminal 201 to the Vss terminal 202. Similarly, the p-channel MOS transistor 221, upon source-to-drain breakdown thereof, assumes a bipolar transistor function thereby to cause a current to flow from the Vdd terminal 201 to the Vss terminal 202.
When a negative high voltage enters through the Vdd terminal 201, both the n-channel MOS transistor 211 and the p-channel MOS transistor 221 function as forward-biased diodes, so as to protect the internal circuit 208 by causing the current due to the negative voltage to flow in the forward direction of the diodes implemented by the MOS transistors.
It is to be noted, however, that the protective circuit 204 of the conventional semiconductor device may fail to function when a positive voltage enters through the Vdd terminal 201, as will be detailed below. Since the destruction voltage of the gate insulation film of the CMOS transistor is generally around 1V/1 nm (10 MV/cm), the gate insulation film having a lower thickness of around 5 nm, as used in the recent semiconductor device, has a destruction voltage of about 5V. When a positive voltage enters through the Vdd terminal, as described above, the source-to-drain breakdown of the MOS transistor triggers the bipolar transistor function.
It is generally difficult, however, to achieve the breakdown voltage which is below 5V in the MOS transistor without causing increase of a leakage current in the MOS transistor. That is, the source-to-drain breakdown voltage is determined by the profile of a p-n junction, and particularly by the impurity concentration and the impurity profile on the lightly-doped side of the p-n junction. Although the source-to-drain breakdown voltage generally decreases if the impurity concentration on the lightly-doped side becomes higher, this is accompanied by an increase in the junction leakage current which flows even when the breakdown voltage is not reached. Therefore, it is not a practical solution to simply decrease the source-to-drain breakdown voltage of the MOS transistors in the protective circuit.
In view of the above, it is an object of the present invention to provide a protective circuit which operates at a voltage higher than the power source voltage and below the breakdown voltage of the internal circuit, substantially without causing an increase of the junction leakage current in the MOS transistor in the protective circuit.
In one embodiment of the present invention, a semiconductor device includes a first source terminal, a second source terminal, an internal circuit including at least one functional MOS transistor having a specific function, a first source line connecting the first source terminal and the internal circuit, a second source line connecting the second source terminal and the internal circuit, and a protective circuit including a protective MOS transistor having a gate, a source, and a drain directly connected to the gate and the first source line, and a bipolar transistor having an emitter connected to the second source line, a collector connected to the first source line and a base directly connected to the source of the n-channel MOS transistor, the protective MOS transistor having a threshold voltage having an absolute magnitude which is higher than a voltage between the first source line and the second source line.
In accordance with the semiconductor device of the one embodiment of the present invention, if a positive noise voltage having an absolute magnitude higher than the threshold voltage of the protective MOS transistor enters through the first source terminal, the noise voltage turns on the protective MOS transistor, which then turns on the bipolar transistor due to the forward bias of the p-n junction in the bipolar transistor. The turn-on of the bipolar transistor passes a current from the first source line toward the second source line, limiting the voltage applied to the internal circuit.
If a negative noise voltage enters through the first source terminal, the p-n junction between the drain and the well of the protective MOS transistor is forward biased, thereby passing a current from the second source line toward the first source line to limit the voltage applied to the internal circuit.
In the one embodiment of the present invention, the first source line may be either a power source line (higher-voltage source line) or a ground line (lower-voltage source line), and the second source line may be a ground line or a power source line depending on the first source line. The protective MOS transistor is implemented by an n-channel transistor if the first source line is a power source line, and is implemented by a p-channel transistor if the first source line is a ground line. The bipolar transistor is implemented by an n-p-n transistor if the first source line is a power source line, and is implemented by a p-n-p transistor if the first source line is a ground line.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.